Multiple module processing system with reset system independent of reset characteristics of the modules
US6480967B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 1999 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | May 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reset module operates in conjunction with a system clock module to provide a combination of reset and clock assertions that can be relied upon to reset conventional processing modules having a variety of reset architectures. A reset command initiates an assertion of the reset signal and an activation of all clocks at the system level. After a predetermined number of clock cycles, the system level clocks are deactivated, and then the reset signal is de-asserted. By providing multiple clock cycles with the reset signal asserted, processing modules having either asynchronous and synchronous reset will be reset. By disabling the clocks before de-asserting the reset signal, the likelihood of a timing hazard caused by an interaction of the reset signal and a clocking signal is reduced or eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.