Algorithm and methodology for the polygonalization of sparse circuit schematics
US6480995B1 · kind B1 · utility
31Cited by
13References
21Claims
0Family size
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Key dates
| Filing date | Apr 14, 1997 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Apr 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An method of creating a physical layout of an integrated circuit. A schematic file (600) is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file (600). The method takes advantage of constraints on the schematic design to provide the layout file (675) quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.