Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip

US6482698B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Daniela Peschiaroli · Milano, IT
• Alfonso Maurelli · Vimercate, IT
• Elisabetta Palumbo · Bernareggio, IT
• Fausto Piazza · Grenoble, FR

Key dates

• Filing date: Mar 26, 2001
• Grant date: Nov 19, 2002
• Expiry date: Mar 26, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/47

Abstract

A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.