Test simulation of a read/write head
US6483298B2 · kind B2 · utility
6Cited by
15References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Jun 1, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49048
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A test simulation circuit includes a simulated read/write head with a magnet shield and a magnetoresistive sensor exposed at a lapped surface. The test simulation circuit also includes first and second electrical test path connected respectively to the magnet shield and the magnetoresistive sensor. The second electrical test path is electrically isolated from the first electrical test path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.