Digital phase control using first and second delay lines
US6483360B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Aug 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase control method phase shifts a predetermined number of clock signals having the same frequency and having different phases at high precision and at high resolution as a whole with its phase interval maintained to keep a predetermined interval. The digital phase control method comprises the steps of preparing fourteen first multi-phase clock signals having a fixed phase, of preparing sixteen second multi-phase clock signals, of phase locking a specific clock signal of the fourteen first multi-phase clock signals with a particular clock signal of the sixteen second multi-phase clock signals, and of changing a combination of the specific and the particular clock signals to be phase-locked to phase shift the second multi-phase clock signals. In addition, in order to generate the second multi-phase clock signals, a delay line comprising ring-shaped chained delay buffers may be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.