Ladder type clock network for reducing skew of clock signals
US6483364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2001 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | May 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A ladder type clock network for reducing the skew of clock signals is provided. The clock network includes a buffer for buffering a clock signal, first delay units for delaying the output of the first buffer by a set time, second buffers connected to respective outputs of the first delay units, and second delay units connected to respective outputs of the second buffers. The first delay units and the second delay units consist essentially of the resistance and capacitance of lines through which the clock signal propagates. Accordingly, the skew of the internal clock signals is reduced, and internal clock signals having a stable duty with respect to variations in a semiconductor device manufacturing process, temperature, and power supply voltage, are generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.