Circuit for controlling a power MOS transistor and detecting a load in series with the transistor
US6483370B1 · kind B1 · utility
2Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2000 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Jul 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit, using a delay determined taking into account the detection with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time is controlled with the power transistor switching time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.