Phase and frequency detector providing immunity to missing input clock pulses
US6483389B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2001 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Jul 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improvement to a phase and frequency detector (PFD) employs an additional reset control that acts to effectively reset the registers that generate the phase indicator signals if an undesirable preconditioned state has been entered. The additional reset control signal is generated by a register that is enabled upon detection of the preconditioned state. The new reset control signal is activated upon detection of a synchronizing signal, that is based on an input source signal, while the enable control is active. The improved detector can allows a phase locked loop (PLL) system locking to the nearest input reference clock edge and it can provide immunity to missing input clock edges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.