Integrated circuit test systems that use direct current signals and impedance elements to improve test signal transmission speed and reduce test signal distortion
US6483758B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1999 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Sep 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuit test systems include an input driver having an output terminal that is connected to a test system port and a biasing device that is connected between the test system port and a reference voltage. The biasing device comprises a Thévenin equivalent circuit that is represented by an impedance element and a nonzero power source. The impedance element may be used to match the impedance of a device under test, which can reduce distortion in signals passed between the device under test and the test system. Furthermore, the power source may be used to provide direct current (DC) signals at the pins of a device under test, which can allow the swing height (e.g., amplitude or magnitude) of the test signals to be reduced. That is, the test signals are superimposed upon the DC voltages to allow “high” and “low” logic levels to be manifested via relatively minor swings in the test signals. By reducing the swing height of the test signals, transmission speed can be improved thereby reducing round trip signal delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.