Phase-locked loop circuitry for programmable logic devices
US6483886B1 · kind B1 · utility
48Cited by
31References
39Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 4, 1999 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Aug 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedback loop and one for the PLL output—one allows the user to adjust the phase of the output relative to that of the input. Similarly, by providing loadable pre-scale (divide by N), post-scale (divide by K) and feedback-scale (divide by M) counters, one allows the user to adjust the frequency of the output to be M/(NK) times that of the input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.