Low cost multiplier block with chain capability
US6484194B1 · kind B1 · utility
3Cited by
9References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1999 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Jun 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This application describes a method of multiplying numbers represented in multiple-word chains. The multiplication scheme allows for the multiplication of both signed and unsigned numbers of varying lengths. The multiplier block 30 executes a 17-bit by 17-bit two's complement multiply and multiply-accumulate in a single instruction cycle. A 4-bit shift value register with a 4 to 16 bit decoder 35 allows the multiplier to do a 1-16 bit barrel shift on either a 16-bit operand or an (N×16)-bit chain operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.