Method and apparatus for data compression and decompression for a data processor system
US6484228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2001 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Nov 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.