Unified multilevel memory system architecture which supports both cache and addressable SRAM
US6484237B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Oct 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus is embodied in a single integrated circuit. The data processing apparatus includes a central processing unit, at least one level one cache, a level two unified cache and a directly addressable memory. The at least one level one cache preferably includes a level one instruction cache temporarily storing program instructions for execution by the central processing unit and a level one data cache temporarily storing data for manipulation by said central processing unit. The level two unified cache and the directly addressable memory are preferably embodied in a single memory selectively configurable as a part level two unified cache and a part directly addressable memory. The single integrated circuit data processing apparatus further includes a direct memory access unit connected to the directly addressable memory and adapted for connection to an external memory. The direct memory access unit controls data transfer between the directly addressable memory and the external memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.