Clock gated bus keeper
US6484267B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1999 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Dec 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4077
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention comprises a clocked bus keeper circuit that does not drive the bus during the first half of a clock cycle and then holds the value driven onto the bus during the first half of the clock cycle for the second half of the clock cycle. Accordingly, true data drivers on the bus drive the bus during the first half of the clock cycle without the need to overcome the value driven by the bus keeper, but during the second half of the clock cycle, the bus keeper holds the data driven during the first half of the clock cycle. In this manner, there is no bus contention between the true bus data drivers and the bus keeper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.