Integrated EJTAG external bus interface
US6484273B1 · kind B1 · utility
13Cited by
14References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 29, 2000 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Nov 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a processor and an interface. The processor may be configured to support system-on-chip debugging. The interface circuit may be coupled to the processor and configured to interface with an external bus. Reading and writing commands of the processor may be integrated with the system-on-chip debugging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.