System and method for interfacing data with a test access port of a processor
US6484275B1 · kind B1 · utility
4Cited by
12References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1999 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Nov 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2733
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor in accordance with the present invention includes memory that stores test data and control data. The processor also includes a test application that transmits the test data and the control data from the processor's memory to a test access port of the processor. The test access port then utilizes the test data and the control data to capture state data that defines at least one state of the processor while the processor is executing. This test data may be analyzed via conventional techniques to detect and isolate errors in the execution of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.