Dual damascene process using an oxide liner for a dielectric barrier layer
US6486059B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2001 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Apr 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual damascene process is applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. An in-situ oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, and then the excess conductive layer outside the trench level is polished away by a CMP process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.