Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units
US6486705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2001 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | May 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution sinks, and/or between logic paths that are in series. Each of the delay elements ‘steals’ a portion of a clock cycle (and perhaps one or more full clock cycles) from subsequent circuits to provide a more reliable logical function, and to avoid the need for overall additional clock cycles. These fractional cycle stealing elements offer a signal skew adjustment at the sinks of the distribution with no additional routing congestion expense. The disclosed cycle stealing delay elements are programmable, and enable clock skew between individual distribution sinks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.