Logic circuit and its forming method
US6486708B2 · kind B2 · utility
6Cited by
12References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2002 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Apr 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.