Use of search lines as global bitlines in a cam design
US6487101B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2001 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Oct 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure for a content addressable memory (CAM) array having a plurality of memory cells. Each of the memory cells has capacitive storage devices, transistors connected to the storage devices, a wordline connected to and controlling the transistors, bitlines connected to the storage devices through the transistors, combined search and global bitlines connected to the capacitive storage devices. These cells are further arranged into columns, each containing multiplexers connected to the combined search and global bitlines, data-in lines connected to the multiplexers, and search-data lines connected to the multiplexers. Further, the multiplexers select between the data-in lines and the search-data lines to allow the combined search and global bitlines to be alternatively used as data lines and search lines. Also, in the invention each of the columns further has drivers between the multiplexers and the combined search and global bitlines. The drivers drive signals between the multiplexers and the combined search and global bitlines during search and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.