Single-event upset tolerant latch for sense amplifiers
US6487134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2001 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Aug 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series. The second set of dual-path inverters is coupled to the second set of isolation transistors, and the second set of dual-path inverters includes a fifth transistor connected to a sixth transistor in series along with a seventh transistor connected to an eighth transistor in series. The isolation transistor couples the first and second sets of dual-path inverters to ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.