ATM communications system and ATM testing method
US6487215B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1999 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Mar 11, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5658
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An ATM signal generator generates packet signals by linking N data blocks that includes user data and a specifier byte containing a sequence number bit. A transmitter receives the packet signals, generates control signals containing length information, generates N−1 ATM cells accommodating one data block in the payload, generates one ATM cell accommodating one data block and a control signal in the payload, and transmits all of the ATM cells to a communications path. A receiver receives ATM cells from the communications path, detects the number of cell rejections using the sequence number bits extracted from the specifier bytes in all of the ATM cells, and detects the number of bit error occurrences using the length information extracted from the control signals. Sequence number bits are accommodated in all of the ATM cells, and length information is accommodated in the N'th ATM cell, wherefore bit errors and cell rejections can be detected from end to end and the number of cell rejections can be detected even when data containing control signals have been lost on the communications path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.