Peripheral component interface with multiple data channels and reduced latency over a system area network
US6487628B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1999 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral control interface provides access to a system area network for a plurality of peripheral devices connected to the PCI through an I/O bus. A plurality of virtual data channels is defined in local memory to which outstanding requests from peripherals are assigned. Physical channel engines implement the order requests through the assigned virtual data channel with accessed data stored in local memory. A subsequent request by a peripheral can then be immediately fulfilled from data stored in memory. Data channel context stored in memory includes the number of outstanding requests by a user to whom the channel is dedicated, and a physical channel engine can pre-fetch data in response to a plurality of outstanding requests from a peripheral thereby eliminating latency in fulfilling requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.