Area efficient bond pad placement
US6489688B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2001 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | May 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide flip-chip bond pad arrangements that lead to a smaller increase in die size than conventional approaches. This is accomplished by using the core side of a periphery I/O pad ring for placing some of the bond pads in order to meet the bond pad pitch requirements of flip chip technology. For example, alternating bond pads are moved inward to the core side of the I/O pads or drivers, to meet the bond pad pitch requirement between the bond pads that are moved to the core side as well the bond pads that remain outside of the core. Because the bond pads are moved inward instead of outward, the increase in the die size from the edge of the I/O pad ring is reduced. In an alternative embodiment, the bond pads are each bonded on top of an active circuitry of a corresponding I/O pad. In another alternative embodiment, the bond pads are disposed between I/O pads which are spaced from each other by a spacing in the direction of the periphery of the core to accommodate the bond pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.