Method and apparatus for testing image sensing circuit arrays
US6489798B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2000 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N17/002
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for testing an image sensor array such as a C-MOS imager which has sensing circuits arranged in rows and columns and wherein the sensing circuits include photosensitive devices is described. A reset voltage is applied to the photosensitive device in each of the sensor circuits such that at least adjacent circuits are reset to different voltage levels. The voltage on each photosensitive device is detected and compared to an expected level to determine if and where any faults may exist in the sensing circuits or lines in the array. A different reset voltage may be applied to each of the sensor circuits, however in one embodiment, a supply with only two voltage levels may be used. One voltage level is applied to every second column to provide a supply voltage to the photosensitive devices and to every second row to generate a reset enable signal for the photosensitive devices. The second voltage level is applied to the remaining columns and rows resulting in different reset voltage levels on adjacent sensing circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.