Method and apparatus for distributing clocks
US6489820B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Sep 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Insertion delay associated with receiving and distributing a clock within an IC is removed using a DLL. The structure of a differential receiver in the feedback circuit of the DLL is substantially matched to the structure of an input differential receiver which receives and inputs a differential input clock into the DLL. In this manner, the insertion delay associated with the input differential receiver is removed from a delay-corrected clock output from the DLL. By substantially matching one or more aspects of the feedback circuit to one or more aspects of a clock distribution circuit for distributing the delay-corrected clock, the insertion delay associated with the clock distribution circuit can also be removed from the delay-corrected clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.