Variable duty cycle resampling circuits and methods and sample rate converters using the same
US6489901B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2001 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Aug 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0294
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sample rate converter 210, 209 includes a filter 210 for processing digital data in response to a clock controlled by a clock enable signal, the filter 210 receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry 209 generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.