Flushing stale data from a PCI bus system read prefetch buffer
US6490647B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2000 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Apr 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for flushing stale data from a read prefetch buffer of a PCI bus system which transfers data in the form of data streams of contiguous blocks. The PCI bus system comprises a channel adapter at one PCI bus that issues read commands, a data source coupled to a second PCI bus, and a prefetch buffer that prefetches the blocks of read data. A prefetch counter posts the remaining number blocks to be read and transferred, posting the prefetch count at a storage location of a storage memory mapped to a prefetch location in the prefetch buffer. The prefetch count is written to the storage location by a prefetch count write command. The system for flushing stale data from the prefetch buffer comprises a key detector for sensing an unique identifier of the prefetch count write command. Data path logic responds to the key detector, determining the prefetch location of the prefetch buffer from the mapped storage location of the prefetch count write command, and flushing any prefetch data at the determined prefetch location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.