Memory device
US6490649B2 · kind B2 · utility
121Cited by
4References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2002 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Feb 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An addressable memory device for storing blocks of varying length, utilizes a write pointer (18) to indicate the address of the next location to which data are to be written and an erase pointer (16) to indicate the address of the next location from which data are to be erased. It has a sector header (20) appended to each group of data containing information (38) indicating the length of the corresponding sector of data, and the location stored by the write pointer (14), which is selected to ensure that there is always at least one erased block adjacent to the current write block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.