Processor, compiling apparatus, and compile program recorded on a recording medium
US6490673B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1999 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Nov 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each of registers R0 to R31 is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit 431 outputs information to the selectors 4321 and 4322 on the registers and the locations (upper and lower areas) in which data is written by the instructions that have issued in one cycle. Each of the selectors 4321 and 4322 selects one out of pieces of data that have been output from first, second, and third arithmetic operation units 44, 45, and 46 and writes the selected data in the upper or lower area in one register. A dependency analysis unit 110 in a compiling apparatus considers the upper and lower registers in one 64-bit register as separate resources, analyzes the data dependency relations between the instructions, and generates a dependency graph that indicates the data dependency relations. A instruction rearrangement unit 111 rearranges the instructions and generates execution codes using the dependency graph.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.