Method for manufacturing semiconductor device capable of suppressing narrow channel width effect
US6492220B2 · kind B2 · utility
10Cited by
8References
42Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 25, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | May 25, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for manufacturing a semiconductor device, a shallow trench isolation layer made of silicon oxide is formed in a semiconductor substrate to partition an area for forming a MOS transistor. Then, first impurities are introduced into the MOS transistor forming area to adjust a threshold voltage of the MOS transistor. Then, second impurities are introduced into end portions of the MOS transistor forming area of the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.