Semiconductor device
US6492727B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 17, 2001 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Aug 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside of the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.