Programmable logic device with highly routable interconnect
US6492834B1 · kind B1 · utility
66Cited by
50References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2001 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Feb 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (200) comprises an input multiplexer region (504), logic elements (300), input-output pins (516), and output multiplexer region (508).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.