Patent · US Expired

Digital driver circuit

US6492847B1 · kind B1 · utility

5Cited by
4References
7Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 12, 2000
Grant dateDec 10, 2002
Priority date
Expiry dateOct 12, 2020

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K5/133
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.