Power-on reset circuit generating reset signal for different power-on signals
US6492848B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Jun 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a semiconductor device; and, more particularly, to a power-on reset circuit to produce a stable reset signal irrespective of driving speed of a power-on signal which is applied thereto at the time of its initial chip operation. The power-on reset circuit according to the present invention comprises an input unit receiving the power-on signal from an external circuit; a schmitt trigger inverter including an output node, wherein a voltage level at the output node is toggled from a high voltage level signal to a low voltage level signal before an output signal from the input unit increases up to a desired voltage level; and an output unit coupled to the output node for generating the power-on reset signal in response to the voltage level at the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.