Electronic circuit with bulk biasing for providing accurate electronically controlled resistance
US6492866B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1998 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Apr 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for generating an electronically controlled electrical resistance by apparatus of at least one MOS transistor. A source-drain junction of the MOS transistor is used for the generation of the electrical resistance between a first and a second terminal, in order to optimize the linearity of the electrical resistance, there have been provided means for generating a bulk signal, which apparatus generate from the voltage on that terminal of the circuit arrangement which is coupled to the source electrode of an associated MOS transistor a signal for driving a bulk electrode of the associated MOS transistor, which signal is generated from the voltage on the terminal and an additionally superposed direct voltage of such a polarity that, depending on the doping type of the MOS transistor the formation of a diode between the source and bulk regions of this MOS transistor is avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.