Low power analog equalizer with variable op-amp gain
US6492876B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2001 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Oct 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G5/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a variable resistor capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.