Reconfigurable frame counter
US6493359B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1999 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | May 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The invention provides an apparatus, and related method, for providing a reconfigurable frame counter that can accommodate differing start of frame pulse locations in a synchronous communication system. The frame counter may be integrated with existing devices thus providing a cost effective advance in the functionality of existing communication devices. The reconfigurable frame counter includes a multiplexer, a byte processor and a frame counter. The multiplexer byte interleave multiplexes a plurality of lower data rate SONET signals to generate a higher data rate SONET signal of framed data bytes. The byte processor processes transport overhead bytes of the higher data rate SONET signal in accordance with a frame byte count value. The frame byte counter counts clock pulses that are each associated with the arrival of a framed data byte and generates a frame byte count value that corresponds to a frame byte location of the currently received framed data byte. The frame byte counter has a programmable configuration start address value and a synchronization pulse input and, in response to a synchronization pulse on the synchronization pulse input, the frame byte counter counts the c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.