Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit
US6493741B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1999 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Oct 1, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.