Method and apparatus for scheduling and using memory calibrations to reduce memory errors in high speed memory devices
US6493836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | May 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or frequency of soft memory errors is provided to control logic in a memory controller, which intelligently modifies the frequency of memory calibration cycles based on the detected memory errors. Thus, in response to an unacceptable number of memory errors, the memory controller may increase the frequency of calibration cycles. The memory controller may include error checking logic that monitors memory errors on multiple memory channels, if multiple memory channel are provided, to enable the memory controller to modify calibration frequency on a channel-by-channel basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.