Method and apparatus for indentifying causes of poor silicon-to-simulation correlation
US6493851B1 · kind B1 · utility
7Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2001 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Jul 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method identifies the cause of poor correlation between an integrated circuit model and measured integrated circuit performance. The method includes determining the propagation delays through two separate integrated circuit components. The propagation delays are then compared to each other to identify the cause of the poor correlation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.