Integrated circuit block model representation hierarchical handling of timing exceptions
US6493864B1 · kind B1 · utility
11Cited by
4References
88Claims
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Key dates
| Filing date | Jun 20, 2001 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Jun 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a block model abstraction of an integrated circuit developed from a hierarchal netlist, the hierarchal handling of timing exceptions is accomplished by selecting certain nodes not viewable at the top level in accordance with a set of rules, and raising these nodes to the top level so that defined timing exceptions may be applied. The timing model is next generated, and exception signatures created for paths between the selected nodes. Signatures are then removed from paths were such signature would not otherwise be valid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.