Pulsed circuit topology including a pulsed, domino flip-flop
US6496038B1 · kind B1 · utility
34Cited by
31References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pulsed circuit topology including a pulsed domino flip-flop. A circuit includes a domino logic gate having a domino output node responsive to input data during an evaluate pulse. Reset circuitry initiates and self-terminates a reset pulse during which the domino output node is precharged. A latch responsive to a first pulsed clock input signal is provided to latch data indicated at the domino output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.