System and method for accurate adjustment of discrete integrated circuit delay lines
US6496048B1 · kind B1 · utility
6Cited by
17References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Jul 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00097
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method of controlling delay in a delay line. In a delay line having a system mode and an oscillator mode, wherein the delay line delays a signal as a function of a delay code, the method comprises setting the delay code, placing the delay line in oscillator mode, determining frequency of oscillation of the delay line, comparing the frequency of oscillation to a target frequency and adjusting the delay code until the frequency of oscillation of the delay line is substantially equal to the target frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.