Modular architecture for image transposition memory using synchronous DRAM
US6496192B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1999 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Aug 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/2628
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture for a video transpose memory employs SDRAM memory devices which are arranged in memory rows such that elements in a single row may be accessed without memory set-up latency. The memory architecture includes at least two memory banks such that memory write operations to one bank may be interleaved with memory write operations to the other bank. Samples of the image along one direction are stored into the memory in groups such that corresponding samples in the orthogonal direction are held in the same memory row. The memory banks are interleaved on the store operation such that consecutive write operations access respective memory rows in the alternating memory banks. The number of samples in a group of samples is selected such that the total time for displaying the number of samples in the group is at least equal to the set-up latency of the memory. Accordingly, consecutive groups of samples may be stored into the alternating memory banks continuously. When image data are read from memory, the memory read operations are not interleaved. To compensate for the set-up latency in the read operations, the controller advances the first read operation for a particular…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.