Content addressable memory
US6496398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2001 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Dec 6, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to content addressable memory (CAM), particularly, to a CAM having its memory array, which contains a plurality of memory locations, being divided into at least a first and a second memory block (100, 102), whereby the first and second memory block (100, 102) are formed by a first and second portion of each of said memory locations, respectively. The CAM further comprises a first set of compare lines (115) and a first set-of match lines (116) associated to said first memory block (100), and a second set of compare lines (117) and a second set of match lines (118) associated to said second memory block (102), and pre-charge units (112, 114) for charging said match lines before a comparison operation. The present invention provides an improved CAM which allows flagging of memory locations of which the content only partially matches a given comparison value. This is achieved by a CAM according to the above features using the pre-charge state of the match lines (116, 118) as a logically valid state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.