Method and apparatus for generating and controlling integrated circuit memory write signals
US6496424B2 · kind B2 · utility
2Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | Apr 20, 2001 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Apr 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for generating a write enable pulse that is independent of the clock duty cycle and the clock frequency. The circuit includes a pulse generator for generating a pulse in response to a clock signal and a write enable signal generator for generating a write enable pulse. The pulse tracks the leading edge of the clock signal. A logic circuit is coupled to the pulse generator and the write enable signal generator to generate the write enable pulse by combining the pulse and the write enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.