Semiconductor device and semiconductor device testing method
US6496433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2001 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Jan 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a normal mode and a test mode for testing the semiconductor device, and is provided with a first circuit which receives an input signal, a test signal and an output enable signal, and outputs the input signal in response to the output enable signal, a second circuit which is coupled to the first circuit and outputs the input signal obtained from the first circuit, and power supply pads which receive a power supply voltage which is supplied in common to the first circuit and the second circuit. The first circuit fixes an output impedance of the second circuit to a high-impedance regardless of the output enable signal when the test signal indicates the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.