Semiconductor memory device having altered clock frequency for address and/or command signals, and memory module and system having the same
US6496445B2 · kind B2 · utility
18Cited by
5References
44Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 5, 2001 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Sep 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a clock buffer which receives an external clock signal and generates a first internal clock signal having a frequency lower than that of the external clock signal and a second internal clock signal having a frequency which is the same as that of the external clock signal. An address buffer, command signal buffer and/or register receive respective input signals at a timing of the first internal clock signal. On the other hand, a data buffer inputs/outputs data at a timing of the second internal clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.