Digital FM receiver employing combined sample-and-hold and integrate-and-dump detectors for improved bit error rates
US6496547B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1999 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Nov 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2275
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A narrow-band digital frequency-modulation (FM) limiter-discriminator (LD) receiver with two independent detectors that combine to remove most of the bit errors caused by FM-clicks in an encoded channel. The output of the LD circuit is presented to a sample-and-hold (S&H) detector and to an integrate and dump (I&D) detector. Because the S&H and I&D detector outputs are offset in time by one-half bit and they are not entirely correlated, an error in one does not necessarily imply an error in the other. Using convolutional coding and Viterbi decoding, with threshold-compensation of the I&D detector output and threshold- or envelope-compensation of the S&H detector output, averaging the two compensated detector signals improves the receiver bit error rate (BER) performance by more than 3 dB over the soft-decision thresholded I&D detector alone, which until now was believed to be optimum in the art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.